- 5 Resultados
precio mínimo: € 160,49, precio máximo: € 212,81, precio promedio: € 190,75
1
Modeling of Electrical Overstress in Integrated Circuits by Carlos H. Diaz Hardcover | Indigo Chapters
Pedir
por Indigo.ca
C$ 285,95
(aprox. € 209,38)
PedirEnlace patrocinado

Modeling of Electrical Overstress in Integrated Circuits by Carlos H. Diaz Hardcover | Indigo Chapters - libro nuevo

ISBN: 9780792395058

Electrical overstress (EOS) and Electrostatic discharge (ESD) pose one of the most dominant threats to integrated circuits (ICs). These reliability concerns are becoming more serious with… Más…

new in stock. Gastos de envío:zzgl. Versandkosten., más gastos de envío
2
Modeling of Electrical Overstress in Integrated Circuits
Pedir
por Indigo.ca
C$ 285,95
(aprox. € 212,81)
PedirEnlace patrocinado
Modeling of Electrical Overstress in Integrated Circuits - libro nuevo

ISBN: 9780792395058

Electrical overstress (EOS) and Electrostatic discharge (ESD) pose one of the most dominant threats to integrated circuits (ICs). These reliability concerns are becoming more serious wi… Más…

new in stock. Gastos de envío:zzgl. Versandkosten., más gastos de envío
3
Modeling of Electrical Overstress in Integrated Circuits
Pedir
por Springer.com
€ 160,49
Envío: € 0,001
PedirEnlace patrocinado
Modeling of Electrical Overstress in Integrated Circuits - libro nuevo

ISBN: 9780792395058

Electrical overstress (EOS) and Electrostatic discharge (ESD) pose one of the most dominant threats to integrated circuits (ICs). These reliability concerns are becoming more serious with… Más…

Nr. 978-0-7923-9505-8. Gastos de envío:Worldwide free shipping, , DE. (EUR 0.00)
4
Modeling of Electrical Overstress in Integrated Circuits - Carlos H. Diaz/ Charvaka Duvvury/ Sung-Mo (Steve) Kang/ Sung-Mo Kang
Pedir
por Hugendubel.de
€ 181,99
Envío: € 0,001
PedirEnlace patrocinado
Carlos H. Diaz/ Charvaka Duvvury/ Sung-Mo (Steve) Kang/ Sung-Mo Kang:
Modeling of Electrical Overstress in Integrated Circuits - encuadernado, tapa blanda

ISBN: 0792395050

Modeling of Electrical Overstress in Integrated Circuits ab 181.99 € als gebundene Ausgabe: Auflage 1995. Aus dem Bereich: Bücher, Wissenschaft, Technik, Medien > Bücher, Springer US

Nr. 4044454. Gastos de envío:, , DE. (EUR 0.00)
5
Modeling of Electrical Overstress in Integrated Circuits - Diaz, Carlos H.; Duvvury, Charvaka; Sung-Mo (Steve) Kang
Pedir
por Achtung-Buecher.de
€ 189,07
Envío: € 0,001
PedirEnlace patrocinado
Diaz, Carlos H.; Duvvury, Charvaka; Sung-Mo (Steve) Kang:
Modeling of Electrical Overstress in Integrated Circuits - encuadernado, tapa blanda

1994, ISBN: 0792395050

1995 Gebundene Ausgabe Elektrotechnik, VLSI; Development; integratedcircuit; Material; Semiconductor; semiconductordevices; Simulation; tables; testing, mit Schutzumschlag 11, [PU:Sprin… Más…

Gastos de envío:Versandkostenfrei innerhalb der BRD. (EUR 0.00) MARZIES.de Buch- und Medienhandel, 14621 Schönwalde-Glien

1Dado que algunas plataformas no nos comunican las condiciones de envío y éstas pueden depender del país de entrega, del precio de compra, del peso y tamaño del artículo, de una posible membresía a la plataforma, de una entrega directa por parte de la plataforma o a través de un tercero (Marketplace), etc., es posible que los gastos de envío indicados por eurolibro/terralibro no concuerden con los de la plataforma ofertante.

Datos bibliográficos del mejor libro coincidente

Detalles del libro
Modeling of Electrical Overstress in Integrated Circuits by Carlos H. Diaz Hardcover | Indigo Chapters

Electrical overstress (EOS) and Electrostatic discharge (ESD) pose one of the most dominant threats to integrated circuits (ICs). These reliability concerns are becoming more serious with the downward scaling of device feature sizes. Modeling of Electrical Overstress in Integrated Circuits presents a comprehensive analysis of EOS/ESD-related failures in I/O protection devices in integrated circuits. The design of I/O protection circuits has been done in a hit-or-miss way due to the lack of systematic analysis tools and concrete design guidelines. In general, the development of on-chip protection structures is a lengthy expensive iterative process that involves tester design, fabrication, testing and redesign. When the technology is changed, the same process has to be repeated almost entirely. This can be attributed to the lack of efficient CAD tools capable of simulating the device behavior up to the onset of failure which is a 3-D electrothermal problem. For these reasons, it is important to develop and use an adequate measure of the EOS robustness of integrated circuits in order to address the on-chip EOS protection issue. Fundamental understanding of the physical phenomena leading to device failures under ESD/EOS events is needed for the development of device models and CAD tools that can efficiently describe the device behavior up to the onset of thermal failure. Modeling of Electrical Overstress in Integrated Circuits is for VLSI designers and reliability engineers, particularly those who are working on the development of EOS/ESD analysis tools. CAD engineers working on development of circuit level and device level electrothermal simulators will also benefit from the material covered. This book will also be of interest to researchers and first and second year graduate students working in semiconductor devices and IC reliability fields.

Detalles del libro - Modeling of Electrical Overstress in Integrated Circuits by Carlos H. Diaz Hardcover | Indigo Chapters


EAN (ISBN-13): 9780792395058
ISBN (ISBN-10): 0792395050
Tapa dura
Año de publicación: 1994
Editorial: Carlos H. Diaz
178 Páginas
Peso: 0,438 kg
Idioma: eng/Englisch

Libro en la base de datos desde 2007-11-06T11:07:32-06:00 (Mexico City)
Página de detalles modificada por última vez el 2023-09-27T05:01:24-06:00 (Mexico City)
ISBN/EAN: 9780792395058

ISBN - escritura alterna:
0-7923-9505-0, 978-0-7923-9505-8
Mode alterno de escritura y términos de búsqueda relacionados:
Autor del libro: carlos, diaz diaz, kim sung, kang
Título del libro: modeling electrical overstress integrated circuits, integrated science, springer


Datos del la editorial

Autor: Carlos H. Diaz; Sung-Mo (Steve) Kang; Charvaka Duvvury
Título: The Springer International Series in Engineering and Computer Science; Modeling of Electrical Overstress in Integrated Circuits
Editorial: Springer; Springer US
148 Páginas
Año de publicación: 1994-11-30
New York; NY; US
Idioma: Inglés
160,49 € (DE)
164,99 € (AT)
177,00 CHF (CH)
Available
XXV, 148 p.

BB; Hardcover, Softcover / Technik/Elektronik, Elektrotechnik, Nachrichtentechnik; Schaltkreise und Komponenten (Bauteile); Verstehen; VLSI; development; integrated circuit; material; modeling; semiconductor; semiconductor devices; simulation; tables; testing; Electronic Circuits and Systems; Electrical and Electronic Engineering; Elektrotechnik; BC

1 Electrical Overstress in ICS.- 1.1 Definition of Electrostatic Discharge Phenomena.- 1.2 Impact of ESD on IC Chip Technologies.- 1.3 Protection Strategies for Reducing ESD Effects.- 1.4 ESD Models and Qualification.- 1.5 EOS Models and Qualification.- 1.6 Previous Work on ESD/EOS Device Failure Modeling.- 2 NMOS ESD Protection Devices and Process Related Issues.- 2.1 ESD Phenomena in nMOS Devices.- 2.2 Failure Modes in nMOS.- 2.3 Protection Technique Using nMOS Device Structures.- 2.4 The Impact of Process Technologies on nMOS ESD Behavior.- 2.5 Advance nMOS Device Protection Concepts.- 3 Measuring EOS Robustness in ICS.- 3.1 Statistical Distribution of EOS/ESD-related Failures.- 3.2 Characterization of Bipolar Devices.- 3.3 EOS Characterization of nMOS Devices.- 3.4 Summary.- 4 Eos Thermal Failure Simulation for Integrated Circuits.- 4.1 Nomenclature.- 4.2 ITSIM: A Nonlinear Thermal Failure Simulator for ICs.- 4.3 Simulation Results for Ceramic and Plastic Packages.- 4.4 Summary.- 5 ITSIM: A Nonlinear 2D - 1D Thermal Simulator.- 5.1 Introduction.- 5.2 Running the Program.- 5.3 Input File.- 5.4 An Example.- 6 2D Electrothermal Analysis of Device Failure in Mos Processes.- 6.1 Device Level Electrothermal Simulation.- 6.2 Comparison of Experimental and 2D Electrothermal Results.- 6.3 Summary.- 7 Circuit-Level Electrothermal Simulation.- 7.1 Temperature Effects and Device Models.- 7.2 Simulation of Avalanche Breakdown.- 7.3 Temperature Model for Electrothermal Simulation.- 7.4 iETSIM: An Electrothermal Circuit-Level Simulation Tool.- 7.5 Summary.- 8 IETSIM : An Electrothermal Circuit Simulator.- 8.1 Introduction.- 8.2 Running the Program.- 8.3 Input File: Circuit Description and Format.- 8.4 Low Temperature Thermometer Example.- 9 Summary and Future Research.- 9.1 Summary.- 9.2 Future Research.- About the Authors.

< para archivar...