Hardware Acceleration of EDA Algorithms - libro nuevo

EAN (ISBN-13): 9781441909435
ISBN (ISBN-10): 1441909435
Tapa dura
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Año de publicación: 2010
Editorial: Springer Nature Singapore
194 Páginas
Peso: 0,469 kg
Idioma: eng/Englisch

Libro en la base de datos desde 2009-08-31T12:52:02-05:00 (Mexico City)
Página de detalles modificada por última vez el 2024-03-08T10:21:59-06:00 (Mexico City)
ISBN/EAN: 1441909435

ISBN - escritura alterna:
1-4419-0943-5, 978-1-4419-0943-5
Mode alterno de escritura y términos de búsqueda relacionados:
Autor del libro: sunil, gula, gulat
Título del libro: eda, hardware, algorithms, gpu

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Datos del la editorial

Autor: Sunil P Khatri; Kanupriya Gulati
Título: Hardware Acceleration of EDA Algorithms - Custom ICs, FPGAs and GPUs
Editorial: Springer; Springer US
192 Páginas
Año de publicación: 2010-04-06
New York; NY; US
Impreso en
Idioma: Inglés
106,99 € (DE)
109,99 € (AT)
118,00 CHF (CH)
POD
XXII, 192 p.

BB; Hardcover, Softcover / Technik/Elektronik, Elektrotechnik, Nachrichtentechnik; Schaltkreise und Komponenten (Bauteile); Verstehen; FPGA; Field Programmable Gate Array; algorithms; architecture; computer-aided design (CAD); integrated circuit; micro-alloy transistor, MAT; model; simulation; static-induction transistor; Electronic Circuits and Systems; Computer-Aided Engineering (CAD, CAE) and Design; Computer-Aided Design (CAD); BC

Hardware Acceleration of EDA Algorithms: Custom ICs, FPGAs and GPUs Kanupriya Gulati Sunil P. Khatri This book deals with the acceleration of EDA algorithms using hardware platforms such as Custom ICs, FPGAs and GPUs. Widely applied CAD algorithms are studied for potential acceleration on these platforms. Coverage includes discussion of conditions under which it is preferable to use one platform over another, e.g., when an EDA problem has a high degree of data parallelism, the GPU is typically the preferred platform, whereas when the problem has more control, an FPGA may be preferred. Results are presented for the acceleration of several CAD algorithms (fault simulation, fault table generation, model card evaluation in SPICE, Monte Carlo based statistical static timing analysis, Boolean Satisfiability), demonstrating speedups up to 800X compared to single-core implementatinos of these algorithms. This book serves as a valuable guide on how best to leverage parallelism to accelerate CAD algorithms. It also presents a methodology to automatically extract SIMD parallelism from regular uniprocessor code which satisfies a set of constraints. With this approach, such uniprocessor code can automatically be converted to GPU code, allowing for significant acceleration. This approach is particularly useful since different GPUs have vastly different specifications, making the manual generation of GPU code an unscalable proposition. In particular, this book: Provides guidelines on whether to use Custom ICs, GPUs or FPGAs when accelerating a given EDA algorithm, validating these suggestions with a concrete example (Boolean Satisfiability) implemented on all these platforms; Demonstrates the acceleration of several popular EDA algorithms on GPUs, with speedups up to 800X; Helps the reader by presenting example algorithmswhich may be used by the reader to determine how best to accelerate their specific EDA algorithm; Discusses an automatic approach to generate GPU code, given regular uniprocessor code which satisfies a set of constraints; Serves as a valuable reference for anyone interested in exploring alternative hardware platforms for accelerating various EDA applications by harnessing the parallelism available in these platforms.
Provides guidelines on whether to use GPUs or FPGAs when accelerating a given EDA algorithm, with validation by a concrete example implemented on both platforms Demonstrates the acceleration of several popular EDA algorithms on GPUs, with speedups from 30X to 800X Presents techniques in a way that the reader can use example algorithms presented to determine how best to accelerate their specific EDA algorithm Discusses an automatic approach to generate GPU code, given regular uniprocessor code Includes supplementary material: sn.pub/extras